Semiconductor devices, such as microprocessors, stand-alone and embedded memory devices, voltage reference circuits, power management circuits etc., require a certain sequence of operations to be run immediately after the power supply voltage has been turned on. Such sequence of operations is commonly known as a power up sequence. The power up sequence may include for example, resetting of storage elements (e.g. latches, flip-flops, registers), starting oscillators (e.g. in pumping power sources or PLLs), and enabling internal voltage sources or references in a particular order. The sequence normally takes a significant amount of time to complete, and starts after the power supply voltage has reached a certain minimum voltage level. The sequence normally does not have to be re-run until the power supply voltage has dropped below the minimum level. For most electronic devices, it is also important to have a stable and reliable power supply to ensure proper operation of logic functions, like pumping circuits, memory storage elements and other blocks that are sensitive to power supply voltage variations and it is important to know if the power supply voltage level accidentally drops below a certain level at any given time during operation. In other words, sometime power supply voltage level needs to be monitored.
The dependability of the power supply is especially important for instance in mobile applications where the power supply is a battery with a finite amount of amper-hours between recharges. A circuit typically used for assessing or monitoring the power supply voltage level and initiating a power up sequence in semiconductor devices is typically called power up detection circuit or power voltage (level) detector, or simply a power up circuit. The power up circuit monitors the voltage level of a power source, such as Vdd or Vcc power voltages, or input/output circuitry power supply voltage, and generates an active flag signal indicative of the voltage level being above the minimum required level. The supply voltage sensitive circuits use this active flag signal to either initiate or continue operation.
FIG. 1 is a circuit schematic of a prior art power up circuit. In this example the circuit is used for detecting the Vdd power supply voltage level. Power up circuit 10 includes a voltage divider circuit and a delay circuit. The voltage divider circuit consists of p-channel transistor 12, p-channel transistor 14 with its gate terminal connected to its drain terminal, commonly known to those of skill in the art as a diode connection, and resistor 16, all connected serially between the power supply Vdd and ground (Vss). P-channel transistor 12 has its gate terminal connected to a deep power down signal DEEP_PD for disconnecting Vdd from the voltage divider circuit. The delay circuit includes a series of inverters 18, 20, 22 and 24 connected between the common node of transistor 14 and resistor 16, and output PWR_OK. The output PWR_OK in the present example represents the active flag signal, where a high voltage level indicates that the Vdd power supply voltage is above the minimum level. Capacitors 26 and 28 are connected to the input terminals of inverters 12 and 16.
The operation of power up circuit 10 is as follows: after Vdd has been turned on, the Vdd voltage level starts increasing from ground or Vss to the Vdd nominal value. Those of skill in the art will understand that nominal voltages depend upon the particular application and/or circuit, but the embodiments of the present invention can be applied to monitoring any type of power supply voltage on a semiconductor device. While the Vdd voltage ramps up, signal DEEP_PD is held at the low voltage level of Vss or logic low, and direct current flows from Vdd through the DC path of transistors 12 and 14 and resistor 16. The input terminal of inverter 18 rises towards Vdd voltage level or logic high, and eventually reaches a voltage level that changes the output of inverter 18 from a logic high to a logic low voltage level. This changing of states propagates through the remaining inverters to drive PWR_OK to the logic high voltage level. In this example, PWR_OK at the high logic voltage level indicates that the Vdd voltage has reached and is maintained above a certain level sufficient for the power voltage level sensitive blocks to initiate or continue their safe operation.
Most battery-powered semiconductor devices have power saving modes to help reduce power consumption of the devices. One of the commonly known power saving modes is a deep power down mode. In the deep power down mode, the device is essentially turned off, where retention of data and logic states of circuit blocks is not required and quick return to normal operation is not expected. Therefore, monitoring of the power supply voltage level in the deep power down mode is not necessary. When the deep power down mode is entered in the example of FIG. 1, DEEP_PD is driven to the high logic voltage level, transistor 12 turns off and the Vdd node is decoupled from the voltage divider circuit. This effectively disables power up circuit 10, which is thus unable to track the Vdd voltage level, and results in PWR_OK eventually changing to the Vss low voltage level. It is important to note that in deep power-down mode power supply (e.g. Vdd, Vcc etc.) may or may not be turned off.
Another commonly known and more frequently used power saving mode is a standby mode, also referred to as a sleep mode. In the sleep mode, essential circuits, such as data storage elements (e.g. RAM, registers), reference sources, clock management circuits (e.g. DLL or PLL) remain powered, so that the device can return to an active mode in a relatively shorter time. In sleep mode, as well as in the normal operation mode, it is most often required that PWR_OK remains at the enabling voltage level to keep the essential circuits active and to prevent unnecessary initiation of the power sequence. At the same time, it is important to minimize power consumption and to disable every current consumption path that is not required for operation or for preserving logic states.
There are several problems with the presently known power up circuit 10 shown in FIG. 1. The voltage divider circuit will draw current from the Vdd supply as long as DEEP_PD is at the low voltage level. The current through the voltage divider circuit in power up circuit 10 can be cut off only when DEEP_PD is at the high voltage level, that is, only when the device is in the deep power down mode.
Also, the prior art circuity of FIG. 1 does not have provisions for maintaining the sleep mode. Replacing the DEEP_PD with a sleep mode signal, or logically combining them would still result in the input terminal of inverter 18 discharging towards Vss when a power saving mode is entered and the DC path through the voltage divider circuit is cut off. The PWR_OK signal then drops to the low voltage level Vss. Consequently reentering the normal mode of operation will require a relatively long amount of time, since the entire power up sequence of the device will be re-run. Therefore, in the circuit of FIG. 1, transistor 12 must remain on during the sleep mode in order to keep the PWR_OK signal level high, current will be drawn through the voltage divider circuit. Although only a few microamperes of current normally consumed by a power up circuit, such as power up circuit 10 of FIG. 1, is very important for battery-powered applications.
Power conservation being critical for mobile products, power saving modes as previously discussed should be used frequently.
By example, conventional comparator circuits such as the dual mode comparator circuit shown in FIG. 2 has a normal and power saving mode of operation, where the power saving mode is used to maintain circuit functionality with minimum current consumption when circuit reaction time is not critical. The dual mode comparator circuit of FIG. 2 includes a normal differential circuit and a low power differential circuit. The normal differential circuit includes p-channel transistors 50 and 52 arranged in a current mirror configuration, n-channel input transistors 54 and 56, and n-channel current source transistor 58. Input transistor 54 receives signal VREF, input transistor 56 receives input signal VIN, while the gate terminal of current source transistor 58 receives a bias voltage VBIAS. VBIAS voltage is generated from the circuit consisting of transistors 60 and 62 connected in series between Vdd and Vss, where transistor 60 is controlled by signal SLEEP, and transistor 62 is connected in a diode configuration. A disable circuit consisting of n-channel transistor 64 that couples VBIAS to a low power supply rail Vss in response to signal SLEEP. The low power differential circuit includes p-channel transistors 66 and 68 arranged in a current mirror configuration, n-channel input transistors 70 and 72, and n-channel current source transistor 74. Input transistor 70 and the gate terminal of transistor 74 receives VREF, and input transistor 72 receives input signal VIN. It is noted that transistor 74 is sized to draw substantially less current than transistor 58.
In normal or high-speed operation, the SLEEP signal is set to the low voltage level such that both the normal differential and the low power differential circuits are turned on. In the low power mode of operation where speed is not critical, the SLEEP signal is set to the high voltage level to turn off the normal differential circuit by setting VBIAS to the Vss voltage level. Therefore, comparator functionality is still maintained, but with lower power consumption and longer response time than compared to the normal mode of operation.
In the case of the dual mode comparator circuit of FIG. 2, the time needed for recovery of the comparator from sleep mode is relatively short since activation of the normal differential circuit is immediate upon changing the state of the SLEEP signal from logic high to logic low.
In the case of power up circuits, it is important to ensure the short recovery time of the entire chip because it is unlikely that mobile device users will accept long wait periods for bringing their device from a power saving mode to the normal operation due to the time consuming re-running of power up sequences. One way to balance power conservation and time to return to normal operation after exiting a power saving mode, is to exit the power saving modes without re-running the power up sequence.